OMOWUYI OMONIYI OLAJIDE2023-09-222023-09-22https://teras.ng/api/asset/document/18bb068a-c060-482b-8b1d-4670461b1f75https://teras.ng/catalog-item/6ea6d526-2d78-40de-9f8f-58fe945b4044http://dspace.teras-network.net:4000/handle/123456789/37283This dissertation presents the development of a non-binary error control decoder for solid state drives that require high throughput when reading data for error correction. The miniaturization of chip fabrication has made flash memory cells of Solid State Drives (SSDs) susceptible to distortion and error. This is as a result of the continuous storage of bits unto a single cell, which eventually leads to an increase in the number of errors to be corrected by the decoder. Also, the representation of the messages passed between the variable node and the check node involve the use of large Galois fields, which eventually results in very high decoding complexity without leading to an increase in the decoding throughput. Bose-Chaudhuri-Hocquenghem (BCH) code previously utilized to correct multi-bit errors, causes the SSD controller to experience latency during decoding. In this work, a non-binary Low Density Parity Check (LDPC) code is used in conjunction with a small Galois Field (GF) of eight, a parallel architecture and a reduced iteration limit to develop an error control decoder for SSDs. The error control decoder was synthesized on a ZYNQ 7000 Series Field Programmable Gate Array (FPGA). The developed error control decoder achieved a throughput of 2.34Gbps at 125-MHz clock frequency and a maximum iteration limit of six (6). A total power of 0.223W was consumed by the decoder. The result shows an improvement in the throughput by 7.3%, and an increase in the power by 5.2% when compared with the decoder implemented by Toriyama et al 2018.Post Graduate Theses